1. Field of the Invention
The invention relates to DC/DC regulation using NMOS and PMOS transistors as pass devices, and more particularly to the use of two output voltage regulation loops, where a current sense buffer triggers the second voltage regulation loop.
2. Description of the Related Art
Linear regulators are used in many electronic devices and applications for converting an unregulated input voltage, typically a low voltage input, to a regulated output voltage. One particular implementation of a linear voltage regulator is referred to as a low dropout (LDO) regulator. Such a LDO regulator is a DC linear voltage regulator, it generally operates with a very small input-output differential voltage across the regulator and offers a well regulated voltage at its output terminal. Usually a LDO regulator consists of a feedback-controlled loop connected to a transistor (or transistors). The feedback-controlled loop typically comprises a differential amplifier (error amplifier). The feedback-controlled loop controls the gate voltage of the transistor and thereby its impedance. Depending on the gate voltage, the transistor supplies a different amount of current to the LDO's output terminal. The gate voltage is modulated such that the regulator provides a steady DC voltage regardless of load conditions or input transients.
FIG. 1 shows a circuit of the conventional art including an NMOS pass transistor 31 and a PMOS pass transistor 32, a voltage divider 35, and error amplifiers 33 and 34 using a common Vref input. NMOS pass transistor 31 and PMOS pass transistor 32 are coupled in parallel between voltage input Vin and voltage output Vo. Coupled between Vo and ground is voltage divider 35 with resistors 351, 352, and 353. The junction VFB1 between resistors 351 and 352 is coupled to the +input of error amplifier 34. The junction VFB2 between resistors 352 and 353 is coupled to the −input of error amplifier 33. The outputs of error amplifiers 33 and 34 drive the gate G of NMOS pass transistor 31 and PMOS pass transistor 32, respectively. The disadvantages of the circuit of FIG. 1 are:
The circuit of FIG. 1, with the two feedback voltages VFB1 and VFB2, has the NMOS pass device always on when VFB1>VFB2. When VFB2≦VREF, the PMOS is turned on only when the output voltage Vo drops such that VFB1≦VREF. The disadvantage of this circuit is that it is very dependent on the offset of the two error amplifiers 33 and 34 and on the accuracy of the voltage divider 35 to minimize the output drop voltage necessary to turn the PMOS on. This circuit will basically have two possible output voltages Vo, depending on the output load current.
FIG. 2 is another circuit of the conventional art and similar to FIG. 1, except that two reference voltages VR1, VR2 and two resistors 41, 42 are used. Its disadvantages are: The circuit of FIG. 2 has only one feedback voltage but still two error amplifiers 33 and 34 to drive the NMOS 31 and PMOS 32 pass devices. The output voltage Vo is regulated in this case to the same value from the two error amplifiers 33 and 34 but a small offset between the two regulating (feedback) loops will make the circuit unstable.
U.S. patent applications and U.S. Pat. Nos. which have a bearing on the present invention are:
U.S. Patent Application 2009/0189577 (Lin et al.) describes an LDO linear regulator including a PMOS power transistor having a variable size, where its size is adjustable by a control signal. The control signal is an N-bit digital signal generated by an analog-to-digital converter. In addition a variable current source can be used, driven by the same analog-to-digital converter.
U.S. Patent Application 2009/0115382 (Hasegawa et al.) discloses a Low Drop-Out/Linear Drop-Out regulator having a PMOS output transistor Tr1, an error amplifier, a buffer amplifier and a drive capability adjustment transistor PMOS Tr3. A second PMOS transistor Tr2 provides feedback to the buffer amplifier.
U.S. Pat. No. 7,521,909 (Dow et al.) shows a linear regulator comprising a pass element, transistor 24, an error amplifier 23, a buffer 33, a sense network 28 (a voltage divider) and a Miller compensation circuit 40. Transistor 24 is formed to include a main transistor which forms a sense current that is representative of the current through transistor 24.
U.S. Pat. No. 6,229,289 (Piovaccari et al.) teaches a regulator which switches between a switched mode and linear regulator (LDO) mode. The linear regulator controls a first transistor coupled between input Vin and output Vout. The switched mode controller, a Pulse Width Modulation controller, controls a second transistor which, in series with an inductor, is also coupled between input Vin and output Vout.
U.S. Pat. No. 7,531,996 (Yang et al.) presents an LDO which includes an NMOS and a PMOS transistor coupled in parallel between supply power and output. First and second error amplifiers drive the NMOS and the PMOS transistor, respectively. A voltage divider provides the input(s) to the error amplifiers.
It should be noted that none of the above-cited examples of the related art provide the advantages of the below described invention.